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Exploring Innovation| ISSN:2347-6389(Online)| Reg. No.:15318/BPL/13| Published by BEIESP| Impact Factor:3.76
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Volume-1, Issue-7 June 18, 2014
26
Volume-1, Issue-7 June 18, 2014

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Volume-1 Issue-7, June 2014, ISSN: 2347-6389 (Online)
Published By: Blue Eyes Intelligence Engineering & Sciences Publication Pvt. Ltd.

 

Page No.

1.

Authors:

To-Po Wang, Yen-Chu Lee

Paper Title:

Design of Effective Noise Cancellation Circuits in Acoustic

Abstract: This paper presents an effective noise cancellation circuit in acoustic, which is designed, simulated, and measured. The feedforward earphone is with high performance of noise suppression. The main structure consists of a controller, a notch filter, a high-pass filter, a microphone, and a speaker. The noise detection microphones pick up sounds and divide them into human voice and low-frequency noise. After passing through the gain-controlled filters, the embedded filtered-X least mean-square (FxLMS) algorithm will generate anti-noise signals with 180° phase difference to ambient noise. Consequently, these anti-noise signals will be transformed from digital formats to analog format, and thereby transformed to acoustic signal by the speakers. The generated acoustic signal will cancel the ambient noise, leading to a quiet zone. According to the measured results, it is indicated that a 15-dB noise reduction is achieved.

Keywords:
Active noise cancellation, low-frequency noise, feed forward type, feedback type.


References:

1.   I. T. Ardekani and W. H. Abdulla, “Active noise control in three dimensions,” IEEE Trans. Control Syst. Technol., 2014. (Accepted)
2.   D. C. Chang and F. T. Chu, “Feedforward active noise control with a new variable tap-length and step-size filtered-X LMS algorithm,” IEEE Trans. Audio, Speech, Lang. Process., vol. 22, no. 2, pp. 542-555, Feb. 2014.

3.    D. C. Chang and F. T. Chu, “A new variable tap-length and step-size FxLMS algorithm” IEEE Signal Process. Lett., vol. 22, no. 2, pp. 542-555, Feb. 2014.

4.    M. Guldenschuh and R. D. Callafon, “Detection of secondary-path irregularities in active noise control headphones,” IEEE Trans. Audio, Speech, Lang. Process., vol. 22, no. 7, pp. 1148-1157, July 2014.

5.    S. Ahmed, M. T. Akhtar, and X. Zhang, “Online acoustic feedback mitigation with improved noise-reduction performance in active noise control systems,” IET Signal Processing, vol. 7, Iss. 6, pp. 505-514, Aug. 2013.

6.    http://www.ams.com.


  




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2.

Authors:

Mohammad Bagher Heidari, Zoheir Kord Rostami

Paper Title:

High Performance Current-Mode Multiplier Circuit based on Carbon Nanotube Transistors

Abstract: Carbon Nanotube Field Effect Transistor (CNFET) is a promising new technology that overcomes several limitations of traditional silicon integrated circuit technology. In recent years, the potential of CNFET for analog circuit applications has been explored. This paper proposes a novel four quadrant analog multiplier design using CNFETs. The simulation based on   CNFET technology shows that the proposed multiplier has better features than CMOS Multiplier. Multiplier-divider circuits is using in digital signal processing base on neural networks and communications (amplifiers with variable gain, modulators, detectors and,…).In  Most of CMOS analog circuit, transistors  are only in triode or saturate  regions;  till now both  regions not used. In this one kind of current mode multiplier- divider circuits is intrudused.it is very simple, has low die area and wide range in low voltage. All tough this circuit has no sense to temperature variation and varying parameters.

Keywords:
CNT, Analog signal processing, current- mode operation, multiplier, reconīŦgurable circuits.


References:

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2.        A. Motamed, C. Hwang, and M. Ismail, “A low-voltage low-power wide rang CMOS variable gain amplifier,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process, vol. 45, no. 7, pp. 800–811, Jul. 1998.

3.        C. Popa, Synthesis of Computational Structures for Analog Signal Processing, New York, USA: Springer-Verlag, 2011.

4.        C. Popa, Superior-Order Curvature-Correction Techniques for Voltage References, New York, USA: Springer-Verlag, 2009.

5.        C. Popa, “Low-power CMOS bulk-driven weak-inversion accurate current-mode multiplier/divider circuits,” in Proc. Int. Conf. Electr Electron. Eng., 2003, pp. 66–73.

6.        C. Popa, “Computational circuits using bulk-driven MOS devices,” in Proc. IEEE EUROCON Conf., May 2009, pp. 246–251.

7.        C. Popa, “Logarithmic curvature-corrected weak inversion CMOS voltage reference with improved performances,” presented at the 11th Int. Workshop on Thermal Investigations on ICs and Systems, Lake Maggiore, Italy, 2005.

8.        C. Popa, “A new curvature-corrected voltage reference based on the weight difference of gate-source voltages for subthreshold-operated MOS transistors,” in Proc. Int. Symp. Circuits Syst., 2003, pp. 585–588.

9.        C. C. Chang and S. I. Liu, “Weak inversion four-quadrant multiplier and two-quadrant divider,” Electron. Lett., vol. 34, no. 22, pp. 2079–2080, Oct. 1998.

10.     M. Gravati, M. Valle, G. Ferri, N. Guerrini, and N. Reyes, “A novel current-mode very low power analog CMOS four quadrant multiplier,” in Proc. 31st Eur. Solid-State Circuits Conf., Sep. 2005, pp. 495–498.

11.     C. Popa, “High accuracy CMOS multifunctional structure for analog signal processing,” in Proc. Int. Semicond. Conf., 2009, pp. 427–430.

12.     C. Popa, “CMOS multifunctional computational structure with improved performances,” in Proc. 33th Ed. Annu. Semicond. Conf., vol. 2. 2010, pp. 471–474.

13.     C. Popa, “Multiplier circuit with improved linearity using FGMOS transistors,” in Proc. Int. Symp. ELMAR 2009, pp. 159–162.

14.     Y. H. Kim and S. B. Park, “Four-quadrant CMOS analogue multiplier,” Electron. Lett., vol. 28, no. 7, pp. 649–650, Mar. 1992.

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16.     C. Sawigun and J. Mahattanakul, “A 1.5V, wide-input range, high bandwidth CMOS four-quadrant analog multiplier,” in Proc. IEEE Int. Symp. Circuits Syst., May 2008, pp. 2318–2321.

17.     C. Sawigun, A. Demosthenous, and D. Pal, “A low-voltage, low-power, high-linearity cmos four-quadrant analog multiplier,” in Proc. 18th Eur. Conf. Circuits Theory Design, Aug. 2007, pp. 751–754.

18.     C. Popa, “Improved linearity active resistor with controllable negative resistance,” in Proc. IEEE Int. Conf. Integr. Circuits Design Technol., Aug. 2006, pp. 1–4.

19.     C. Popa and A. M. Manolescu, “CMOS Differential Structure with Improved Linearity and Increased Frequency Response,” in Proc. Int. Semicond. Conf., vol. 2. Sep.–Oct. 2007, pp. 517–520.

20.     C. Popa, “Programmable CMOS active resistor using computational circuits,” in Proc. Int. Semicond. Conf., Oct. 2008, pp. 389–392.

21.     C. Popa, “Improved linearity CMOS active resistor based on the mirroring of the ohm law,” in Proc. IEEE 17th Int. Conf. Electron., Circuits, Syst., Dec. 2010, pp. 450–453.

22.     A. Naderi, H. Mojarrad, H. Ghasemzadeh, A. Khoei, and K. Hadidi, “Four-quadrant CMOS analog multiplier based on new current squarer circuit with high-speed,” in Proc. IEEE EUROCON Conf., May 2009, pp. 282–287.

23.     A. Naderi, A. Khoei, and K. Hadidi, “High speed, low power four quadrant CMOS current-mode multiplier,” in Proc. IEEE Int. Conf. Electron., Circuits Syst., Dec. 2007, pp. 1308–1311.

24.     A. M. Manolescu and C. Popa, “A 2.5GHz CMOS mixer with improved linearity,” J. Circuits, Syst. Comput., vol. 20, no. 2, pp. 233– 242, 2010.

25.     S. I. Liu and Y. S. Hwang, “CMOS squarer and four-quadrant multiplier,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 42, no. 2, pp. 119–122, Feb. 1995.

26.     S. A. Mahmoud, “Low voltage low power wide range fully differential CMOS four-quadrant analog multiplier,” in Proc. 52nd IEEE Int. Midwest Symp. Circuits Syst., Aug. 2009, pp. 130–133.

27.     C. Sawigun and W. A. Serdijn, “Ultra-low-power, class-AB, CMOS four quadrant current multiplier,” Electron. Lett., vol. 45, no. 10, pp. 483–484, May 2009.


 

 

 

 

 

 



 

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